DocumentCode
2634414
Title
Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors
Author
Ashouei, Maryam ; Bhattacharya, Soumendu ; Chatterjee, Abhijit
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
fYear
2007
fDate
6-10 May 2007
Firstpage
125
Lastpage
130
Abstract
It is well known that scaled CMOS technologies are increasingly susceptible to induced soft errors and environmental noise. Probabilistic checksum-based error detection and compensation has been proposed in the past for scaled DSP circuits for which a certain level of inaccuracy can be tolerated as long as system-level quality-of-service (QoS) metrics are satisfied. Although the technique has been shown to be effective in improving the SNR of digital filters, it can only handle errors that occur in the system states. However, the transient-error rate of combinational logic is increasing with technology scaling. Therefore, handling errors in the arithmetic logic circuitry of DSP systems is also essential. This is a significantly more difficult task due to the fact that a single error at the output of an adder or multiplier can propagate to more than one system state causing multiple states to be erroneous. In this paper, a unified scheme that can address probabilistic compensation for errors both in the system states and in the embedded adders and multipliers of DSP filters is developed. It is shown that by careful checksum code design, significant SNR improvements (up to 13 dB) can be obtained for linear filters in the presence of soft errors.
Keywords
CMOS integrated circuits; adders; combinational circuits; digital filters; error compensation; error detection; integrated circuit noise; logic design; multiplying circuits; quality of service; CMOS technologies; arithmetic logic; combinational logic; digital filters; environmental noise; error compensation; error detection; linear filters; operator errors; probabilistic checksum; quality-of-service; soft errors; transient-error rate; Adders; CMOS technology; Circuit noise; Digital filters; Digital signal processing; Logic; Nonlinear filters; Quality of service; Signal to noise ratio; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location
Berkeley, CA
ISSN
1093-0167
Print_ISBN
0-7695-2812-0
Type
conf
DOI
10.1109/VTS.2007.50
Filename
4209901
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