On the impact of gate oxide degradation on SRAM dynamic and static write-ability

Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors. The minimum voltage of operation, V_min, can be limited by any combination of write failure, read disturb failure, access failure and/or retention failure. Of these, the write failure is often observed as the major V_min limiter in sub-50nm processes. In addition, the current generation transistors have high-k metal gate (HKMG) and these are prone to degradation due to higher level of electric field stress. The degradation increases V_min due to increase in dynamic write failures and eventually, static write failures as the supply voltage decreases. We show that there exists a critical breakdown resistance (R_crit) for a given supply voltage at which the SRAM write failure transitions from being dynamically limited to statically limited. For a 32nm low-power SRAM, the value of R_crit increases by ~9X as the supply voltage reduces from 1V to 0.7V. Further, we show that the commonly used SRAM write-assist (WA) techniques do not lower R_crit and can only improve the write-ability when the breakdown resistance, R_sbd, is larger than R_crit.