Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics

We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.