The impact of pipelining on SIMD architectures

This paper explores the fundamental impacts of pipeline technology on massively parallel SIMD architectures. The potential for performance improvement in the instruction delivery is explored, and stall penalties associated with reduction operations are derived. Scheduling mechanisms to mitigate stall cycles are also presented. In addition, the design of pipelined processing elements is considered, and formula for stall penalties, and area costs are constructed. These results indicate that a 5-10 fold improvement in SIMD performance is well within technological limits