WSI architecture for L-U decomposition: a radar array processor

Presents a wafer scale architecture for a radar array processor. The computation intensive block in this processor is the L-U decomposition block, which is amenable to reconfigurable wafer implementation. The authors´ design employs only two types of cells thus facilitating restructuring through laser linking and cutting. Details of these cells are presented as is the mapping of the algorithm to a systolic array architecture. In particular, the authors discuss the internal switches and multiplexers of the multiply-accumulate cell, and the external switches. Also described is the fast reciprocal cell which is expressly developed for this radar processor. Finally, the reconfiguration strategy is discussed