DocumentCode :
2634609
Title :
Test Set Reordering Using the Gate Exhaustive Test Metric
Author :
Cho, Kyoung Youn ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA
fYear :
2007
fDate :
6-10 May 2007
Firstpage :
199
Lastpage :
204
Abstract :
When a test set size is larger than desired, some patterns must be dropped. This paper presents a systematic method to reduce test set size; the method reorders a test set using the gate exhaustive test metric and truncates the test set to the desired size. To determine the effectiveness of the method, test sets with 1,556 test patterns were applied to 140 defective Stanford ELF18 test cores. The original test set required 758 test patterns to detect all defective cores, while the test set reordered using the presented method required 286 test patterns. The method also reduces the test application time for defective cores.
Keywords :
automatic test pattern generation; production testing; ATPG; automatic test pattern generation; gate exhaustive test metric; production testing; test application time; test patterns; test set reordering; Automatic test pattern generation; Automatic testing; Chaos; Costs; Delay; Fault detection; Performance evaluation; Production; System testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-2812-0
Type :
conf
DOI :
10.1109/VTS.2007.79
Filename :
4209913
Link To Document :
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