Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R_SD) reduction. <;100>;-oriented NW channel further improves on-current as compared to <;110>; NW channel. In Pelgrom plot of σV_th of NW Tr., there exists a universal line whose A_vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV_th universal line is eliminated by suppressing R_SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.