Reliability characterization of 32nm high-k metal gate SOI technology with embedded DRAM

Author

Mittl, Steve ; Swift, Ann ; Wu, Ernest ; Ioannou, Dimitris ; Chen, Fen ; Massey, Greg ; Rahim, Nilufa ; Hauser, Mike ; Hyde, Paul ; Lukaitis, Joe ; Rauch, Stew ; Saroop, Sudesh ; Wang, Yanfeng

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2012

fDate

15-19 April 2012

Abstract

The reliability characterization of a high performance 32nm SOI CMOS technology featuring gate first High-K Metal Gate and embedded High-K Metal Fill DRAM is presented. This technology features high performance 0.9V thin dielectric devices and 1.5V thick dielectric I/O devices. Included are results of Hot Carrier, Bias Temperature, Planar and Trench Node TDDB, Gate to Contact, silicon eFUSE, SER, SRAM and Logic circuit reliability evaluations.

Keywords

CMOS memory circuits; DRAM chips; dielectric devices; high-k dielectric thin films; hot carriers; integrated circuit reliability; silicon-on-insulator; SER; SOI CMOS technology; SRAM; bias temperature; embedded high-k metal fill DRAM; high-k metal gate SOI technology; hot carrier; logic circuit reliability evaluation; planar node TDDB; reliability characterization; silicon eFUSE; size 32 nm; thick dielectric I/O device; thin dielectric device; trench node TDDB; voltage 0.9 V; voltage 1.5 V; Dielectrics; Human computer interaction; Logic gates; Metals; Performance evaluation; Random access memory; Stress; BTI; HCI; High-K; Metal Gate; SER; SHE; SRAM; Self Heating; eDRAM; eFUSE;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2012 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4577-1678-2

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2012.6241866

Filename

6241866