DocumentCode :
2634872
Title :
A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications
Author :
Bao, Dan ; Wu, Chuan ; Ying, Yan ; Chen, Yun ; Zeng, Xiao Yang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2011
fDate :
25-28 Jan. 2011
Firstpage :
77
Lastpage :
78
Abstract :
An energy-efficient programmable LDPC decoder is proposed for WiMax and Wi-Fi applications. The proposed decoder is designed with overlapped processing units, flexible message passing network and medium-grain partitioned memories to achieve flexibility, area reduction, and energy efficiency. The decoder can be programmed by host processor with several special-purpose micro-instructions. Thus, various operation modes can be reconfigured. Fabricated in SMIC 0.13μm 1P8M CMOS process, the chip occupies 4.32 mm2 with core area 2.97 mm2, and consumes 170mW with a throughput of 302Mb/s when operating at 145MHz and 1.2V.
Keywords :
CMOS integrated circuits; WiMax; parity check codes; wireless LAN; SMIC 1P8M CMOS process; Wi-Fi applications; WiMax applications; area reduction; bit rate 302 Mbit/s; energy-efficient programmable LDPC decoder; flexible message passing network; frequency 145 MHz; medium-grain partitioned memories; power 170 mW; size 0.13 mum; special-purpose micro-instructions; voltage 1.2 V; Algorithm design and analysis; Decoding; Energy efficiency; IEEE 802.11 Standards; Parity check codes; Throughput; WiMAX;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4244-7515-5
Type :
conf
DOI :
10.1109/ASPDAC.2011.5722293
Filename :
5722293
Link To Document :
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