Title :
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
Author :
Yu, Thomas Edison ; Yoneda, Tomokazu ; Zhao, Danella ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai
Abstract :
This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints
Keywords :
clocks; embedded systems; logic partitioning; logic testing; system-on-chip; IP cores; bandwidth conversion; domain partitioning; embedded core test; gated-clocks; multiple clock domains; optimal test schedules; power constraints; power-aware test wrappers; system-on-chip; test scheduling; wrapper design; Bandwidth; Circuit testing; Cities and towns; Clocks; Design methodology; Embedded computing; Frequency; Information science; Partitioning algorithms; System testing; SoC; embedded core test; multi-clock domain; test scheduling; wrapper design;
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2812-0
DOI :
10.1109/VTS.2007.86
