Title :
Targeted processor architecture for embedded real-time control using δ-operator
Author :
Wu, Xiaofeng ; Sam, Manfred ; Xiao, Size
Author_Institution :
Sch. of Aerosp., Mech. & Mechantronic Eng., Univ. of Sydney, Sydney, NSW, Australia
Abstract :
Control engineers are constantly faced with the challenges in working under time and economical constraints to develop efficient processors in term of speed and size. In light of this, recent developments have seen the advance of System-on-Chip (SoC) solutions which embed all the features of a control system processor onto a single chip. Even recent developments have seen the use of Field Programmable Gate Arrays (FPGAs) allied with simulation software to provide a System-on-Programmable-Chip (SoPC) solution which allows for rapid prototyping, modification, and upgrading of control systems. This paper presents a targeted processor architecture aimed at realizing a controller structure implemented using the δ-operator. By utilizing simulation software and the flexible nature of FPGA prototyping, an optimized Control System Processor (CSP) with an accurate arithmetic model is presented which can be reprogrammed for a variety of control applications.
Keywords :
embedded systems; field programmable gate arrays; microprocessor chips; system-on-chip; δ-operator; FPGA; SoC; arithmetic model; control system processor; embedded real-time control; field programmable gate arrays; rapid prototyping; system-on-chip; system-on-programmable-chip solution; targeted processor architecture; Control systems; Equations; Mathematical model; Process control; Radiation detectors; Random access memory; Read only memory; δ-operator; CSP; SoPC; real-time;
Conference_Titel :
Industrial Electronics and Applications (ICIEA), 2011 6th IEEE Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8754-7
Electronic_ISBN :
pending
DOI :
10.1109/ICIEA.2011.5975690
