Title :
Understanding the impact of transistor-level BTI variability
Author :
Fang, Jianxin ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
Recent work has shown large variations due to bias-temperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.
Keywords :
impact (mechanical); transistors; Monte Carlo simulation; analytical method; bias-temperature instability; downscaling device; size 16 nm; transistor-level BTI impact variability; Charge carrier processes; Degradation; Delay; Digital circuits; Integrated circuit modeling; Monte Carlo methods; Transistors; Bias-Temperature Instability (BTI); Degradation Analysis; Digital Circuit Delay; Variability;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2012.6241887
