Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism

Author

Tsai, Yu-Tzu ; Tsai, Cheng-Chih ; Chien, Cheng-An ; Cheng, Ching-Hwa ; Guo, Jiun-In

Author_Institution

Dept. of Electron. Eng., Feng Chia Univ., Minhsiung, Taiwan

fYear

2011

fDate

25-28 Jan. 2011

Firstpage

85

Lastpage

86

Abstract

The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism is successfully validated using TSMC 0.18 technology. The test chip shows ×2.7 performance improvement compared to the conventional static CMOS logic design.

Keywords

CMOS logic circuits; built-in self test; electronic design automation; integrated circuit design; integrated circuit reliability; logic design; multiplying circuits; pipeline processing; TSMC technology; built-in performance adjustment mechanism; cell-based automatic synthesis flow; circuit reliability; dual-phase high-speed multiplier; dual-phase pipeline circuit design automation; high speed dual phase operation domino circuit; size 0.18 mum; word length 64 bit; Circuit synthesis; Clocks; Delay; Latches; Logic gates; Pipelines; Synchronization; domino circuit; pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4244-7515-5

Type

conf

DOI

10.1109/ASPDAC.2011.5722309

Filename

5722309