SPICE simulations of data path timing margins after dielectric breakdown from gate-to-drain using accurate equivalent circuit models

We show that data path performance failures cannot be predicted solely by the increase in gate current that occurs after dielectric breakdown. Even at gate current levels corresponding to soft breakdown, the increase in NFET threshold voltage and reduction in mobility due to drain-source coupling can give rise to significant timing margin violations in critical data paths to the point where performance requirements are no longer met.