Title :
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})
Author :
Rahaman, H. ; Mathew, J. ; Sikdar, B.K. ; Pradhan, D.K.
Author_Institution :
Dept. of Comput. Sci. & Technol., Bengal Eng. & Sci. Univ., Shidpur
Abstract :
This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique requires only 10 vectors, which is independent of multiplier size, at the cost of 6% (avg.) extra hardware and three control pins. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a built-in self-test (BIST) circuit is proposed for generating test patterns internally. This obviates the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using 0.18mum CMOS technology library from UMC
Keywords :
CMOS logic circuits; Galois fields; built-in self test; fault diagnosis; logic testing; multiplying circuits; public key cryptography; 0.18 micron; BIST; C-testable; CMOS technology; Galois field; UMC; built-in self-test circuit; constant test vectors; error control code; polynomial basis bit parallel multiplier circuits; public key cryptography; stuck-at faults; transition fault testability; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Pins; Polynomials; Public key cryptography; C-testable; Galois field; Multipliers; Transition fault; cryptography; error control code.; polynomials;
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2812-0
DOI :
10.1109/VTS.2007.83