Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Currently, commercially available standard-cell libraries are often unstructured set of cells, suitable for several optimization criteria: speed, power, leakage and area consumption. Exploiting a large number of items makes the synthesis process and the library maintenance quite demanding. By smartly selecting a reduced set of cells, such efforts can be reduced, without critically affecting performance. This paper presents a library-reduction strategy which allows for selecting an arbitrarily small subset of cells, also taking into accounts for the features of the actual synthesis tool. Compaction procedure could be driven by one chief criterion (e.g., orienting compacted library at small area, low-power consumption, high speed circuitry). Library compaction is tuned by means of a large set of benchmark circuits, in order to produce results suitable for general-purpose circuit design. In this paper, the compaction strategy is illustrated, and influence of compaction on circuit synthesis and performance is discussed over a wide range of cases, including different technology nodes and silicon foundries. With respect to full-size library synthesis, performance do not appreciably degrades, and in several cases actually improves. Synthesis time decreases and library maintenance and characterization tasks can be significantly reduced. By analyzing and comparing actual contents of several reduced libraries, general criteria for the design of low cell-count libraries can also be inferred.