Title :
Geyser-2: The second prototype CPU with fine-grained run-time power gating
Author :
Zhao, L. ; Ikebuchi, D. ; Saito, Y. ; Kamata, M. ; Seki, N. ; Kojima, Y. ; Amano, H. ; Koyama, S. ; Hashida, T. ; Umahashi, Y. ; Masuda, D. ; Usami, K. ; Kimura, K. ; Namiki, M. ; Takeda, S. ; Nakamura, H. ; Kondo, M.
Author_Institution :
Keio Univ., Yokohama, Japan
Abstract :
Geyser-2 is the second prototype MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Geyser-l, the first prototype only provides the fine-grained run-time PG core. Although it demonstrated the leakage power reduction on a real chip, the operational frequency is limited at 60MHz because of the limitation of the I/O speed. Geyser-2 with cache and TLB mechanism is implemented to show (1) run-time PG works at least with 200MHz which is commonly used clock for embedded systems, and (2) it is also efficient on the environment with real application programs with an operating system.
Keywords :
cache storage; microprocessor chips; operating systems (computers); reduced instruction set computing; Geyser-2; Geyser-l; I-O speed; MIPS CPU; TLB mechanism; cache mechanism; embedded systems; fine-grained run-time PG core; fine-grained run-time power gating; frequency 200 MHz; frequency 60 MHz; leakage power reduction; operating system; real-application programs; second-prototype CPU; Central Processing Unit; Clocks; Layout; Power demand; Prototypes; Runtime; Transistors;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7515-5
DOI :
10.1109/ASPDAC.2011.5722310
