A VHDL implementation of BIST technique in UART design

Author

Idris, M.Y.I. ; Yaacob, Mashkuri

Author_Institution

Fac. of Comput. Sci. & Information Technol., Malaya Univ., Kuala Lumpur, Malaysia

Volume

4

fYear

2003

fDate

15-17 Oct. 2003

Firstpage

1450

Abstract

To increase reliability, manufacturers must be able to discover a high percentage of defective chips during their testing procedures. This paper would highlight the attention given by most customers who are expecting the designer to include testability features that will increase their product reliability. This paper focuses on the design of a UART chip with embedded built-in-self-test (BIST) architecture using FPGA technology. The paper starts by describing the behavior of UART circuit using VHISC hardware description language (VHDL). In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements.

Keywords

built-in self test; design for testability; field programmable gate arrays; hardware description languages; integrated circuit design; integrated circuit reliability; peripheral interfaces; FPGA technology; embedded built-in-self-test architecture; hardware description language; product reliability; universal asynchronous receive transmit chip; Built-in self-test; Circuit faults; Circuit testing; Costs; Digital systems; Field programmable gate arrays; Hardware design languages; Integrated circuit technology; Logic testing; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2003. Conference on Convergent Technologies for the Asia-Pacific Region

Print_ISBN

0-7803-8162-9

Type

conf

DOI

10.1109/TENCON.2003.1273158

Filename

1273158