Novel Approach to Clock Fault Testing for High Performance Microprocessors

This paper presents a novel approach for testing clock faults for high performance microprocessors. Although such faults have been shown to be likely and could compromise delay fault testing, conventional manufacturing test methodology is unable to guarantee their detection. This paper proposes a modification to the conventional clock buffers allowing standard manufacturing test to detect the faults. This is achieved at the cost of a small increase in area and power consumption of the clock buffers, but with no additional test cost or impact on the microprocessor performance and in-field operation. The approach can be applied to the clock system of any high performance chip or microprocessor.