Design and evaluation of variable stages pipeline processor chip

In order to reduce the energy consumption in high performance computing, variable stages pipeline processor (VSP) is proposed, which improves execution time by dynamically unifying the pipeline stages. The VSP adopts a special pipeline register called an LDS-cell that unifies the pipeline stages and prevents glitch propagation. We fabricate the VSP chip on a Rohm 0.18μm CMOS process and evaluate the energy consumption. The result indicates the VSP can achieve 13% less energy consumption than the conventional approach.