Session Abstract

The common global on-chip bus is becoming a bottleneck in communication bandwidth and power dissipation. Multi-bus approaches provide temporary alleviation, but the longer-term scalable solution is a Network-on-Chip (NOC). A NOC consists of a network of shared communication links and routers, which connect to the various IP cores through Network Interfaces. NOC-based SOC design seems to be moving from the research phase to first industrial prototypes and finally high-volume products. What does this paradigm shift imply for manufacturing test? How should NOCs be tested, and how can the NOC be leveraged as part of the on-chip test infrastructure? In this session, we explore these and other issues related to the combination of NOCs and test.