DocumentCode :
2635410
Title :
Session Abstract
fYear :
2007
fDate :
39203
Firstpage :
477
Lastpage :
478
Abstract :
The common global on-chip bus is becoming a bottleneck in communication bandwidth and power dissipation. Multi-bus approaches provide temporary alleviation, but the longer-term scalable solution is a Network-on-Chip (NOC). A NOC consists of a network of shared communication links and routers, which connect to the various IP cores through Network Interfaces. NOC-based SOC design seems to be moving from the research phase to first industrial prototypes and finally high-volume products. What does this paradigm shift imply for manufacturing test? How should NOCs be tested, and how can the NOC be leveraged as part of the on-chip test infrastructure? In this session, we explore these and other issues related to the combination of NOCs and test.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA, USA
ISSN :
1093-0167
Print_ISBN :
0-7695-2812-0
Type :
conf
DOI :
10.1109/VTS.2007.60
Filename :
4209957
Link To Document :
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