Title :
Test and validation for Monsoon processing elements
Author :
Beckerle, Michael J. ; Papadopoulos, Gregory M.
Abstract :
An aggressive, integrated hardware/software approach for the test and validation of Monsoon processing elements is developed. The strategy comprises three main elements: scan-paths of internal processor state, gate-level simulator of the entire processing element for hardware timing verification, and a novel table-driven instruction-level interpreter. Each of these elements is detailed, and it is shown how they contribute to design, test, validation, and debug
Keywords :
computer testing; parallel machines; program debugging; program interpreters; program testing; Monsoon processing elements; debug; design; gate-level simulator; hardware timing verification; internal processor state; processing element; scan-paths; table-driven instruction-level interpreter; test; validation; Automatic testing; Databases; Decoding; Hardware; Pipelines; Program processors; Software testing; System testing; Timing; Yarn;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139871
