• DocumentCode
    2635832
  • Title

    PLL/PID motor control system by using time-domain operation of PWM signal

  • Author

    Machida, Hidekazu ; Kobayashi, Fuminori

  • Author_Institution
    Maizuru Coll. of Technol., Kyoto
  • fYear
    2007
  • fDate
    17-20 Sept. 2007
  • Firstpage
    100
  • Lastpage
    103
  • Abstract
    In PLL motor speed control systems, PID-type loop filter can improve disturbance sensitivity. In this article, we show that, an existing PI-type PLL/PWM motor speed controller (Machida and Kobayashi, 2002) can be supplemented with addition a difference operation including the I-counter, together with FPGA experimental result.
  • Keywords
    field programmable gate arrays; machine control; phase locked loops; pulse width modulation; sensitivity; three-term control; time-domain analysis; velocity control; FPGA; PID-type loop filter; PLL motor speed control system; PWM signal; disturbance sensitivity; time-domain operation; Electronic mail; Filters; Frequency; Motor drives; Phase locked loops; Pulse width modulation; Servomotors; Three-term control; Time domain analysis; Velocity control; FPGA; PLL; motor speed control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SICE, 2007 Annual Conference
  • Conference_Location
    Takamatsu
  • Print_ISBN
    978-4-907764-27-2
  • Electronic_ISBN
    978-4-907764-27-2
  • Type

    conf

  • DOI
    10.1109/SICE.2007.4420958
  • Filename
    4420958
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2635832