Title :
Temperature dependence of soft error rate in flip-flop designs
Author :
Jagannathan, S. ; Diggins, Z. ; Mahatme, N. ; Loveless, T.D. ; Bhuva, B.L. ; Wen, S.-J. ; Wong, R. ; Massengill, L.W.
Author_Institution :
Dept. of EECS, Vanderbilt Univ., Nashville, TN, USA
Abstract :
The factors affecting the temperature dependence of soft error rates (SER) in flip-flops are investigated. Four different flip-flop designs with varying hardness levels were designed and fabricated in a 40 nm bulk CMOS technology. Neutron experiments show an increase in soft error (SE) failure in time (FIT) rate of over 3X for a temperature range of 25 °C - 110 °C. Alpha experiments show 1.5X increase in SE FIT rate for the same temperature range.
Keywords :
CMOS integrated circuits; flip-flops; logic design; radiation hardening (electronics); bulk CMOS technology; flip-flop designs; hardness levels; soft error rate; temperature 25 degC to 100 degC; temperature dependence; Flip-flops; MOSFET circuits; Neutrons; Shift registers; Temperature; Temperature dependence; Temperature sensors; FIT; SER; flip-flop; soft error; temperature;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2012.6241927
