Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates

We measure neutron-induced SET (Single Event Transient) pulse width distributions from inverter chains with four drive strengths in a 65-nm CMOS process. The SET rates on 16x inverters are 17% and 38% of those on 1x in the twin-and triple-well structures respectively. Our measured results are in line with circuit simulation results that account for bipolar amplification. For higher SET mitigation, clock buffers could be placed adjacent to tap cells to reduce the number of SET pulses caused by the parasitic bipolar effect.