Title :
Reliability Estimation Process
Author :
Koal, T. ; Scheit, D. ; Vierhaus, H.T.
Author_Institution :
Dept. of Comput. Sci., Tech. Univ. of Brandenburg, Cottbus, Germany
Abstract :
The design space of integrated circuits grows due to the need of fault recognition and error compensation. To meet reliability requirements, several reliability increasing methods have to be evaluated. We present a reliability estimation process which allows estimating the resulting reliability of a modified circuit without the need of synthesis. For further speed up, synthesis results after choosing a reliability increasing methods are analyzed. The process is applied to a case study which proves applicability.
Keywords :
integrated circuit design; reliability; error compensation; fault recognition; integrated circuits; modified circuit; reliability estimation process; reliability increasing methods; Aging; Circuit faults; Computational modeling; Electromigration; Hot carrier injection; Integrated circuit modeling; Integrated circuit reliability; Integrated circuit synthesis; Logic design; Negative bias temperature instability; design for reliability; evaluation process; lifetime reliability;
Conference_Titel :
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
Conference_Location :
Patras
Print_ISBN :
978-0-7695-3782-5
DOI :
10.1109/DSD.2009.215
