Deductive Fault Simulation for Asynchronous Sequential Circuits

Fault simulation of the asynchronous sequential circuits is more complicated than fault simulation of their synchronous counterparts. It needs to deal with hazards, oscillations and races. The complex gates in the asynchronous circuits are another challenge especially for deductive fault simulation. In this paper a deductive fault simulator for the speed-independent (SI) asynchronous sequential circuits is presented. The implemented deductive fault simulator was tested using the SI benchmark circuits. The experimental results show significant reduction of the computation time and negligible increase of memory requirements.