A CMOS DC offset cancellation (DOC) circuit for PGA of low IF wireless receivers

Author

Xiangning, Fan ; Yutao, Sun ; Yangyang, Feng

Author_Institution

Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China

Volume

1

fYear

2010

fDate

17-20 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, the sources of DC offset and the corresponding DC offset cancellation techniques are analyzed. A DC negative feedback technique based DC offset canceller (DOC) is designed in details and implemented by SMIC 0.18μm CMOS process. DC offset detector is an important part of DOC. In this paper, an on chip DC offset detection circuit is proposed for the DC negative feedback canceller which can be used in the CMOS programmable gain amplifier (PGA) of a low intermediate frequency (IF) receiver such as IEEE802.15.4/ZigBee wireless sensor network. Post-simulation and chip measurement results show that the DC offset canceller performs well.

Keywords

CMOS integrated circuits; amplifiers; radio receivers; CMOS DC offset cancellation circuit; DC negative feedback technique; DC offset canceller; IEEE 802.15.4-ZigBee wireless sensor network; SMIC CMOS process; low IF wireless receivers; low intermediate frequency receiver; programmable gain amplifier; size 0.18 mum; Attenuation; Closed loop systems; Electronics packaging; Gain; Low pass filters; Receivers; Wireless sensor networks; DC negative feedback; DC offset; DC offset cancellation technique; DC offset canceller; PGA; Wireless receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals Systems and Electronics (ISSSE), 2010 International Symposium on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-6352-7

Type

conf

DOI

10.1109/ISSSE.2010.5607078

Filename

5607078