Synthesizing DSP architectures from behavioral specifications: a formal approach

Author

Elleithy, Khaled M. ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

1131

Abstract

A formal behavioral synthesis framework is introduced for specification, simulation, and synthesis of digital signal processing (DSP) algorithms. The given algorithm is represented using a newly developed language called the algorithm specification language (ASL). The components and connectivity of the synthesized architecture can be represented in three different forms: a language called the realization specification language (RSL), schematic captures, and PROLOG. PROLOG is used as a user interface language between the user subsystem and the synthesis subsystem. Algorithms of linear time complexity are introduced for transferring between different representations

Keywords

computer architecture; computerised signal processing; digital signal processing chips; logic CAD; specification languages; ASL; CAD; DSP architectures; algorithm specification language; behavioral specifications; digital signal processing; formal behavioral synthesis framework; linear time complexity; realization specification language; schematic captures; simulation; user interface language; Circuit testing; Computational modeling; Computer architecture; Digital signal processing; Equations; High level synthesis; Signal synthesis; Specification languages; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112317

Filename

112317