Self-timed logic using current-sensing completion detection (CSCD)

Author

Dean, Mark E. ; Dill, David L. ; Horowitz, Mark

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

187

Lastpage

191

Abstract

A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: reduced parasitic capacitance, removal of spacer tokens in the data stream, and computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison

Keywords

Boolean functions; logic circuits; logic design; Boolean functions; computation state similarity; consecutive data variables; current-sensing completion detection; data stream; dual-rail encoding; logic variable; parasitic capacitance; self-timed circuits; self-timed logic structures; signal wire; silicon area; single-rail variable encoding; spacer tokens; transistors; Boolean functions; CMOS logic circuits; Delay; Encoding; Logic circuits; Logic design; Logic functions; Parasitic capacitance; Silicon; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139878

Filename

139878