Title :
High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic
Author :
García, José C. ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid
Author_Institution :
Inst. for Appl. Microelectron., Univ. of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain
Abstract :
This paper presents the design of a highly efficient CMOS 2-input NAND (gcr-nand). When implemented on a 65 nm CMOS technology, under 1 pF capacitive loading condition, gcr-nand has a lower active area (3.4 times lower), and energy-delay product (56%) than the reference 2-input NAND (lscpl-nand). Furthermore, gcr-nand is able to operate under a high output load.
Keywords :
CMOS integrated circuits; logic circuits; CMOS technology; CMOS two-input NAND; capacitance 1 pF; capacitive loading condition; energy-delay product; high-output load operation; low-race split-level charge-recycling pass-transistor logic; size 65 nm; CMOS logic circuits; CMOS technology; Circuit simulation; Delay; Energy consumption; Energy efficiency; Logic design; Logic gates; Performance loss; Recycling; charge–recycling; high capacitive load; low–energy; low–voltage;
Conference_Titel :
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
Conference_Location :
Patras
Print_ISBN :
978-0-7695-3782-5
DOI :
10.1109/DSD.2009.181
