Generation of finite state machines from parallel program graphs in DIADES

A method is presented for describing parallel program graphs in a high-level synthesis system. Such descriptions are, in general, similar to Karp and Miller parallel program schemata and are more general than Petri nets. It is shown how these graphs are converted to sequential program schemata and then to finite state machines (FSMs) in such a way that the number of states is minimized. The entire FSM synthesizer for control unit synthesis in a comprehensive design automation system is presented and illustrated with a complete example. The synthesizer makes use of inputs and state minimization, state assignment, and logic minimization of FSMs