TCAD/DA for MPU and ASIC development

We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT and delay parameters required in DA works. Effects of statistical process variation on 0.35 μm CMOS have been rigorously characterized with a new global TCAD calibration technique. Based on the data, process variation effects on a 0.25 μm CMOS have been predicted, which is concluded that the Vth and Ids total-variation of the 0.25 μm CMOS shows less than 10% in production process, which is similar with that of the 0.35 μm CMOS