Energy and Performance Model of a SPARC Leon3 Processor

We present a general methodology to implement a processor energy model, based on instruction-level characterization, and we apply it to a SPARC-based Leon3 processor. The model is characterized by simulating back-annotated gate-level netlist and has two levels of accuracy: a coarse-grain estimation based on characterizing each single instruction and a fine-grain estimation accounting for the impact of instructions interdependency on energy and based on characterizing pairs of instructions together. Our investigation also keeps into account the effect that both data switching activity and registers correlation have on energy. We validate our model by applying it to a set of instruction traces generated by instruction set simulation and compare it to extracting energy directly from gate level. We achieve a worst-case error ~12% and a speedup higher than 1000 times.