Amdahl chip delay test system

Author

Deol, I. ; Mallipeddi, C. ; Ramakrishnan, T.

Author_Institution

Amdahl Corp., Sunnyvale, CA, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

200

Lastpage

205

Abstract

The design and implementation of an automatic chip delay test system (CDTS) are described. CDTS has been in use at Amdahl Corporation for over a year and has generated delay tests for about 180 designs ranging from 1000 to 30000 gates, achieving high fault coverage. These designs contain sequential logic and memory elements like random access memories (RAMs). CDTS uses a new scheme for applying delay tests in sequential circuits. The fault model and the delay test generation algorithm used by CDTS are described, and the results of production runs are presented

Keywords

automatic test equipment; automatic testing; delays; fault location; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; Amdahl chip delay test system; automatic chip delay test system; delay test generation algorithm; fault coverage; fault model; gates; memory elements; random access memories; sequential circuits; sequential logic; Automatic testing; Circuit faults; Circuit testing; Delay systems; Logic design; Production; Random access memory; Sequential analysis; Sequential circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139881

Filename

139881