Impact Of Intrinsic Parameter Fluctuations On Deca-nanometer Circuits, And Circuit Modelling Techniques

Device parameter fluctuations - which arise from both the stochastic nature of the manufacturing process, and more fundamentally from the intrinsic discreteness of charge and matter - have become a dominant source of device mismatch in the deca-nanometer regime, and are recognised as a crucial bottleneck to the future yield and performance of circuits and systems. It is likely that a major shift from deterministic design styles to probabilistic design is unavoidable in order to tackle these challenges. Such a change in design style requires the use of statistical compact models, and corresponding techniques for their application. In this paper, a hierarchical device-to-circuit simulation methodology, which can investigate the impact of intrinsic parameter fluctuations on simple circuits has been presented, and its application is demonstrated using a number of examples. These include analyzing the impact of random doping fluctuations on the functionality and reliability of 6-transistor SRAM cells and low swing CMOS circuits. We posit this new approach as a starting point for the design of high quality cell libraries that contain the fluctuation information necessary for design under the constraints of intrinsic parameter fluctuations