DocumentCode
2638047
Title
A simple capacitor votage balancing scheme for the cascaded five-level inverter fed AC machine drive
Author
Chun, T.W. ; Tran, Q.V. ; Lee, Hae ; Kim, H.G. ; Nho, E.C.
Author_Institution
Dept. of Electr. Eng., Univ. of Ulsan, Ulsan, South Korea
fYear
2012
fDate
27-29 March 2012
Firstpage
1
Lastpage
5
Abstract
This paper proposes a simple scheme for balancing the series capacitor voltages at the three-phase cascaded five-level inverter fed an induction motor by using the logic circuits. Using switching patterns based on the multi-carrier technique, two series-capacitor voltages can be only balanced during one cycle. However, they have a ripple voltage, which may cause the induction motor drive to be unstable. The proposed scheme for balancing capacitor voltages can be implemented by simple logic circuits. It can be verified that the series capacitor voltages are maintained constant at wide frequency range through experimental results with 32-bit DSP and Cyclone-III FPGA.
Keywords
digital signal processing chips; field programmable gate arrays; induction motor drives; invertors; power capacitors; Cyclone-III FPGA; DSP; capacitor voltage balancing scheme; induction motor; logic circuits; multicarrier technique; ripple voltage; series-capacitor voltages; switching patterns; three-phase cascaded five-level inverter fed AC machine drive; word length 32 bit; AC machine; Capacitor voltage balance; FPGA; multilevel inverter;
fLanguage
English
Publisher
iet
Conference_Titel
Power Electronics, Machines and Drives (PEMD 2012), 6th IET International Conference on
Conference_Location
Bristol
Electronic_ISBN
978-1-84919-616-1
Type
conf
DOI
10.1049/cp.2012.0234
Filename
6242084
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