DocumentCode
2638093
Title
Optimal architectures for massively parallel implementation of hard real-time beamformers
Author
Watkins, Karen P.
Author_Institution
Appl. Res. Lab., Texas Univ., Austin, TX, USA
Volume
2
fYear
1998
fDate
1-4 Nov. 1998
Firstpage
997
Abstract
This paper reports an experimental analysis of real-time computational architectures applied to digital time delay beamformation. The goal of this research has been to identify the most efficient multiprocessor utilization for a prototypical beamformer by modeling the signal processing and applying selected multiprocessor scheduling algorithms. A synchronous dataflow (SDF) domain model was used to implement the most computationally intense core of the beamformer in Ptolemy. In order to evaluate multiprocessor scheduling performance, four automated scheduling strategies were applied: declustering, a classical list scheduler, dynamic-level scheduler, and a hierarchical scheduler. A manual heuristic schedule was also postulated and evaluated. Several key metrics were applied in judging optimality. It is demonstrated that the hierarchical scheduler holds measurable advantage over the other algorithms considered including the manual method. An analysis of the underlying performance drivers is given.
Keywords
acoustic imaging; acoustic signal processing; array signal processing; data flow computing; image processing; optimisation; parallel algorithms; parallel architectures; processor scheduling; real-time systems; Ptolemy; acoustic imaging; automated scheduling; classical list scheduler; declustering; digital time delay beamformation; dynamic-level scheduler; efficient multiprocessor utilization; experimental analysis; hard real-time beamformers; hierarchical scheduler; manual heuristic schedule; massively parallel implementation; multiprocessor scheduling algorithms; optimal architectures; performance drivers; prototypical beamformer; real-time computational architectures; signal processing; synchronous dataflow domain model; Acoustic measurements; Array signal processing; Computer architecture; Dynamic scheduling; Optimal scheduling; Performance analysis; Processor scheduling; Prototypes; Scheduling algorithm; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-5148-7
Type
conf
DOI
10.1109/ACSSC.1998.751412
Filename
751412
Link To Document