Built-in test using perturbed deterministic patterns

The authors propose a built-in self-test (BIST) structure that uses predefined algorithms to generate perturbed deterministic patterns (PDPs). An on-chip memory and a multiple-input signature register (MISR) are required for this implementation. Using six industrial benchmarks as examples, it is shown that a PDP test generator provides an equivalent or better test coverage compared to a deterministic test generator or a pseudo-random pattern generator. The number of patterns to be stored is much smaller than deterministic patterns. The number of PDPs to be applied to the device-under-test (DUT) is much less than the pseudo-random patterns