Comparing The Performance Of A Low-power High Speed Flip-flop In Bulk And Soi Technologies

Author

Forouzandeh, B. ; Seyedi, A.S.

Author_Institution

Tehran Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

251

Lastpage

255

Abstract

In this paper, the performance of double-edge triggered feedbacked flip-flop (DFFF) in SOI and bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to bulk technology

Keywords

flip-flops; high-speed integrated circuits; logic design; low-power electronics; silicon-on-insulator; SOI technologies; double-edge triggered feedbacked flip-flop; high speed flip-flop; internal node transition; CMOS technology; Circuits; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Latches; Logic; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706578

Filename

1706578