Design Of Fpga-based Multi-operand Modular Adders For Residue Number System Converters

In this paper, the problem of designing binary-to-residue and residue-to-binary converters is investigated, and two new and simple structures of the main processing unit of these converters - the multi-operand modular adder are proposed. The proposed adders, as well as the most known modular adders, use read-only memory (ROM) units for correction of partial results, but are based on a carry-propagate adder tree instead a carry-saved adder tree. Due to dedicated carry logic in the most modern FPGA devices, the response times of the both adder trees, as well as their hardware overheads are nearly equal in a case of their implementation in these devices. However, the ROM volume in the first proposed structure of the multi-operand modular adder, which is destined for constructing of the q-digits R-to-B converters (where q < 8), is up to 8 times lower in comparison with the ROM volume in the known similar adders. The second proposed adder structure allows on further reduction of the ROM volume from O(2^q-1) to O(q) cells, and is destined for constructing of the q-digit R-to-B converters, and q-bit B-to-R converters, when q ges 7