Low Power Encoding in NoCs Based on Coupling Transition Avoidance

Coupling capacitances between adjacent wires in on-chip interconnects significantly affect the amount of power consumption in Ultra-Deep-Submicron technologies. On the other hand, the propagation delay across global on chip interconnects has increasingly become a limiting factor in high-speed design. Crosstalk between adjacent links on the bus contributes a significant portion of this delay. Crosstalk noise also affects the integrity of signals. Decreasing the coupling transitions can improve the side effects of crosstalk noise. We propose an algorithm to minimize the coupling activity transition. We also introduce a new solution to fit the proposed algorithm for network-on-chip (NoC) architecture. The experimental results show that the proposed algorithm reduces the power consumption of NoCs up to 27% in an 8-bit bus.