NBTI-aware design of integrated circuits: a hardware-based approach

Advances in CMOS technology have made possible the increase of integrated circuit´s density, which impacts directly on the performance of the circuit. However, technology scaling poses some reliability concerns. One of the main issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits´ paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of integrated circuits is proposed. In more detail, the technique is based on an on-chip sensor able to monitor integrated circuit aging and to adjust the supply voltage of the circuit in order to minimize NBTI effects. Experimental results obtained throughout simulations demonstrate the technique´s efficiency. Finally, an analysis of the overheads as well as the impact related to process variation renders the evaluation of the proposed approach possible.