Hardware acceleration for rapid prototyping of communication system

Future mobile communication systems incorporate more sophisticated functionalities which improve their performance and increase their complexity. In order to reduce their time to market figure, the simulation time of the prototyping phase has to be improved. This paper presents a solution for improving the prototyping time by using hardware acceleration by means of reconfigurable field programmable gate arrays (FPGA). In this way, it is possible to take advantage of re-programmability and parallel processing features backed up by the hardware in the loop functionality offered through the Matlab environment. As a case of study it has been implemented the encoding and decoding stages of a convolutional Forward Error Correction (FEC) module. The results presented on this paper demonstrates that hardware acceleration based on reconfigurable FPGA helps to reduce the prototyping time by reducing the simulation time needed to validate the behavior of the module under noisy conditions.