A low power 2D DCT chip design using direct 2D algorithm

Author

Chen, Liang-Gee ; Jiu, Juing-Ying ; Chang, Hao-Chieh ; Lee, Yung-Pin ; Ku, Chung-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1998

fDate

10-13 Feb 1998

Firstpage

145

Lastpage

150

Abstract

In this paper, a low power 8×8 2D DCT architecture based on direct 2D approach is proposed. The direct 2D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, a hybrid-architecture adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 μm single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz

Keywords

digital signal processing chips; discrete cosine transforms; logic design; parallel architectures; 2D DCT; 2D DCT chip; 8×8 2D DCT architecture; circuit implementation; computational complexity; critical path simulation; hybrid-architecture adder; Adders; Arithmetic; Chip scale packaging; Circuits; Computational complexity; Computer architecture; Discrete cosine transforms; Energy consumption; Read only memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669434

Filename

669434