Mathematical performance evaluation of mesh Network-on-Chip for VBR flow

Network on chip is an emerging interconnection paradigm to address the scalability of traditional bus architecture. Real-time applications such as multimedia and gaming boxes etc., require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. Theses applications have bring into play a variable bit rate. So guaranteeing critical time need the capability to analyze communication delays in a network on-chip. In this paper, a Network Calculus-based formal is presented. We use this for analyzing the worst delay of NoC switch with RR scheduling by considering peak behavior of flows. The key idea of our proposed method involves presenting and proving a technical proposition to derive delay bound of NoC switch under the mentioned system model.