Abstract :
Grids of metal wires are widely used for distributing the clock signal in large digital circuits. These structures inherently suffer from clock skew, as there always exists some delay between the grid´s perimeter and its center. This paper presents an empirical model of clock skew in square grids. It´s formulated in terms of four parameters: wire resistance, the number of wires, size of buffers driving the grid and the total capacitance of the grid and its load. The model´s accuracy is within 5% of SPICE results for a wide range of grid sizes, wire widths, load capacitances, and other parameters. Also presented are a couple of possible applications in grid design and optimization. As those tasks are iterative, they would take on the order of hours if performed by SPICE-simulating netlists extracted from grid layouts. The proposed model allows reducing the analysis time to less than a second
