DocumentCode
2639107
Title
Decomposed arbiters for large crossbars with multi-queue input buffers
Author
Chi, Hsin-Chou ; Tamir, Yuval
Author_Institution
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
233
Lastpage
238
Abstract
Crossbars are key components of communication switches used to construct multiprocessor interconnection networks. For a fixed number of nodes, larger crossbars result in reduced probability of conflicts and allow packets to traverse the network in fewer hops. However, increasing the size of the crossbar also increases the delay of the arbiter used to resolve conflicting requests. The increased arbitration delay can lead to overall poor network performance. The impact of the increased arbitration delay can be mitigated by decomposing the arbitration process into multiple steps, such that some requests can be granted before the arbitration of the entire crossbar is complete. The design of such decomposed arbiters for larger crossbars is discussed. The focus is on crossbars with multi-queue buffers at their inputs. Such buffers have been shown to provide significantly higher performance than conventional FIFO buffers
Keywords
integrated logic circuits; multiprocessor interconnection networks; queueing theory; switching circuits; communication switches; conflict probability; conflicting requests; crossbars; decomposed arbiters; hops; multi-queue input buffers; multiprocessor interconnection networks; network performance; network traversal; nodes; packets; Buffer storage; Communication switching; Computer science; Delay; Fabrication; Multiprocessor interconnection networks; Packet switching; Switches; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139888
Filename
139888
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