Statistical Power Estimation For Register Transfer Level

In this paper, we propose a macromodeling approach that allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs. Our approach can handle combinational and sequential circuits for register transfer level. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and power dissipation is predicted by a macromodel function. In our experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of just 1%. Our model is parameterizable and provides accurate power estimation