DocumentCode
2639385
Title
Verification Of Digital System By A New Asserting Mechanism Based On Ieee 1500 Sect Standard
Author
Hahanov, V. ; Obrizan, V. ; Hahanova, I. ; Fomina, E.
Author_Institution
Kharkiv Nat. Univ. of Radio Electron.
fYear
2006
fDate
22-24 June 2006
Firstpage
544
Lastpage
548
Abstract
A new technique of assertion mechanism for digital SoC diagnosis and functional verification is proposed. The developed mechanism can be effectively applied on the early stages of design as well as on the implementation phase. The IEEE 1500 SECT standard technologies are used for signals observation
Keywords
IEEE standards; digital circuits; network synthesis; system-on-chip; IEEE 1500 sect standard; SoC diagnosis; asserting mechanism; digital system verification; functional verification; Application specific integrated circuits; Costs; Digital systems; Equations; Hardware; Process design; Redundancy; Software tools; System testing; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location
Gdynia
Print_ISBN
83-922632-2-7
Type
conf
DOI
10.1109/MIXDES.2006.1706639
Filename
1706639
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